Reimplement SSI read using RP2040 PIO state machine
Replace dual-core FIFO bit-bang approach with a dedicated PIO program: - Add ssi.pio: PIO assembly for SSI master (side-set CLK, sample DATA) - Add ssi.pio.h: pioasm-generated C header - ssi_pio_init(): load program, wire CLK/DATA pins, set clock divider - ssi_pio_reconfigure_speed(): live clock-divider update between reads - ssi_pio_read(): push bit-count to TX FIFO, block on RX result word - Remove dual-core headers, FIFO structs, setup1/loop1, requestSsiRead - Bit limit reduced to 1..32 (single PIO ISR word) - TX_DI pin ownership transferred to PIO (no pinMode/digitalWrite)
This commit is contained in:
lucavanstraaten
parent
58a2d37b38
commit
a8633962f2
3 changed files with 140 additions and 81 deletions
148
src/main.cpp
148
src/main.cpp
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@ -1,7 +1,8 @@
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#include <Arduino.h>
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#include <Adafruit_NeoPixel.h>
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#include <hardware/structs/sio.h>
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#include <pico/multicore.h>
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#include <hardware/pio.h>
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#include <hardware/clocks.h>
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#include "ssi.pio.h" // generated from ssi.pio at build time
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// CLOCK module (TX)
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const uint8_t TX_DI = 0;
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@ -17,90 +18,69 @@ const uint8_t RX_RO = 29;
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const uint8_t LED_PIN = 16;
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Adafruit_NeoPixel led(1, LED_PIN, NEO_GRB + NEO_KHZ800);
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// Pre-computed bit masks for the SIO registers.
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// Writing to gpio_set sets a pin HIGH atomically in one cycle.
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// Writing to gpio_clr clears it LOW. Reading gpio_in gives all GPIO states.
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const uint32_t TX_DI_MASK = 1u << TX_DI;
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const uint32_t RX_RO_MASK = 1u << RX_RO;
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// Inter-core protocol
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// Request: [bits:8 | half_us:16 | reserved:8] -> core 1
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// Response: [hi32][lo32][duration_us] -> core 0
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struct SsiRequest {
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uint8_t bits;
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uint16_t half_us;
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};
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struct SsiResponse {
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uint64_t value;
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uint32_t duration_us;
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};
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PIO ssi_pio = pio0;
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uint ssi_sm = 0;
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uint ssi_offset = 0;
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void setStatus(uint8_t r, uint8_t g, uint8_t b) {
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led.setPixelColor(0, led.Color(r, g, b));
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led.show();
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}
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// =========================================================================
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// CORE 1: SSI worker
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// =========================================================================
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void ssi_pio_init(uint half_us) {
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// pioasm generates these helpers in ssi.pio.h
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ssi_offset = pio_add_program(ssi_pio, &ssi_master_program);
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uint64_t ssi_read_core1(uint8_t bits, uint16_t half_us) {
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uint64_t value = 0;
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pio_sm_config c = ssi_master_program_get_default_config(ssi_offset);
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sio_hw->gpio_clr = TX_DI_MASK; // first falling edge: latch
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busy_wait_us_32(half_us);
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// Side-set drives the CLK pin (TX_DI)
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sm_config_set_sideset_pins(&c, TX_DI);
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for (uint8_t i = 0; i < bits; i++) {
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sio_hw->gpio_set = TX_DI_MASK; // rising: encoder shifts
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busy_wait_us_32(half_us);
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sio_hw->gpio_clr = TX_DI_MASK; // falling: sample
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uint32_t bit = (sio_hw->gpio_in & RX_RO_MASK) ? 1 : 0;
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value = (value << 1) | bit;
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busy_wait_us_32(half_us);
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// 'in pins, 1' samples starting at RX_RO
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sm_config_set_in_pins(&c, RX_RO);
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sm_config_set_in_shift(&c, false /* shift_left */, false /* autopush */, 32);
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// 'out x, 32' pulls 32 bits from OSR; shift direction doesn't matter for full word
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sm_config_set_out_shift(&c, true, false, 32);
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// Clock divider: 1 PIO cycle = half_us / 2 microseconds
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// (so that 2 PIO cycles = half_us microseconds = one CLK half-period)
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float div = (float)clock_get_hz(clk_sys) * ((float)half_us / 2.0f) / 1e6f;
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sm_config_set_clkdiv(&c, div);
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// Hand the CLK pin to PIO and set as output
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pio_gpio_init(ssi_pio, TX_DI);
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pio_sm_set_consecutive_pindirs(ssi_pio, ssi_sm, TX_DI, 1, true);
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pio_sm_init(ssi_pio, ssi_sm, ssi_offset, &c);
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pio_sm_set_enabled(ssi_pio, ssi_sm, true);
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}
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sio_hw->gpio_set = TX_DI_MASK; // back to idle
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busy_wait_us_32(30); // monoflop
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void ssi_pio_reconfigure_speed(uint half_us) {
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pio_sm_set_enabled(ssi_pio, ssi_sm, false);
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return value;
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// Drain any leftover words from FIFOs
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pio_sm_clear_fifos(ssi_pio, ssi_sm);
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// Restart SM at the wrap target
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pio_sm_restart(ssi_pio, ssi_sm);
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pio_sm_clkdiv_restart(ssi_pio, ssi_sm);
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float div = (float)clock_get_hz(clk_sys) * ((float)half_us / 2.0f) / 1e6f;
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pio_sm_set_clkdiv(ssi_pio, ssi_sm, div);
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// Jump SM back to the program start
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pio_sm_exec(ssi_pio, ssi_sm, pio_encode_jmp(ssi_offset));
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pio_sm_set_enabled(ssi_pio, ssi_sm, true);
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}
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void setup1() {
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// Core 1 setup: nothing to do, GPIOs already configured by core 0.
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// Importantly: no Serial, no USB, no millis IRQ active here by default
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// when running in this dual-core mode.
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}
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uint32_t ssi_pio_read(uint8_t bits) {
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pio_sm_put_blocking(ssi_pio, ssi_sm, bits - 1);
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uint32_t result = pio_sm_get_blocking(ssi_pio, ssi_sm);
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void loop1() {
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// Block until core 0 sends a packed request word.
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// Word layout: bits in upper 8, half_us in next 16, 8 unused
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uint32_t req = rp2040.fifo.pop();
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uint8_t bits = (req >> 24) & 0xFF;
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uint16_t half_us = (req >> 8) & 0xFFFF;
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uint32_t t0 = time_us_32();
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uint64_t value = ssi_read_core1(bits, half_us);
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uint32_t took = time_us_32() - t0;
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// Push three words back: low32, high32, duration
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rp2040.fifo.push((uint32_t)(value & 0xFFFFFFFF));
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rp2040.fifo.push((uint32_t)(value >> 32));
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rp2040.fifo.push(took);
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}
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// =========================================================================
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// CORE 0: serial command handler
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// =========================================================================
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void requestSsiRead(uint8_t bits, uint16_t half_us, uint64_t& outValue, uint32_t& outTook) {
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uint32_t req = ((uint32_t)bits << 24) | ((uint32_t)half_us << 8);
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rp2040.fifo.push(req);
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uint32_t lo = rp2040.fifo.pop();
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uint32_t hi = rp2040.fifo.pop();
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outTook = rp2040.fifo.pop();
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outValue = ((uint64_t)hi << 32) | lo;
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// ISR shifts left → first bit in MSB. Right-align.
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return result >> (32 - bits);
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}
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void handleCommand(const String& cmd) {
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@ -119,8 +99,8 @@ void handleCommand(const String& cmd) {
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int bits = cmd.substring(firstSpace + 1, secondSpace).toInt();
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int halfUs = cmd.substring(secondSpace + 1).toInt();
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if (bits < 1 || bits > 64) {
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Serial.println("ERR bits must be 1..64");
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if (bits < 1 || bits > 32) {
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Serial.println("ERR bits must be 1..32 (PIO ISR limit)");
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return;
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}
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if (halfUs < 1 || halfUs > 10000) {
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@ -128,13 +108,15 @@ void handleCommand(const String& cmd) {
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return;
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}
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setStatus(0, 0, 16); // blue = reading
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uint64_t value;
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uint32_t took;
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requestSsiRead((uint8_t)bits, (uint16_t)halfUs, value, took);
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setStatus(0, 16, 0); // green = idle
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ssi_pio_reconfigure_speed(halfUs);
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Serial.printf("OK bits=%d half_us=%d hex=0x%llX dec=%llu took=%luus\n",
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setStatus(0, 0, 16);
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uint32_t t0 = micros();
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uint32_t value = ssi_pio_read((uint8_t)bits);
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uint32_t took = micros() - t0;
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setStatus(0, 16, 0);
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Serial.printf("OK bits=%d half_us=%d hex=0x%lX dec=%lu took=%luus\n",
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bits, halfUs, value, value, took);
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}
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@ -143,7 +125,6 @@ void setup() {
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led.begin();
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setStatus(8, 8, 0);
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pinMode(TX_DI, OUTPUT);
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pinMode(TX_DE, OUTPUT); pinMode(TX_RE, OUTPUT);
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pinMode(RX_DE, OUTPUT); pinMode(RX_RE, OUTPUT);
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pinMode(RX_DI, OUTPUT);
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@ -154,11 +135,14 @@ void setup() {
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digitalWrite(RX_DE, LOW);
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digitalWrite(RX_RE, LOW);
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digitalWrite(RX_DI, LOW);
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digitalWrite(TX_DI, HIGH); // SSI idle HIGH
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// TX_DI is owned by PIO - don't pinMode it
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ssi_pio_init(5); // default 5 µs half-period
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delay(200);
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while (!Serial && millis() < 3000) { delay(10); }
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Serial.println("\nSSI bridge ready (dual-core: core 1 dedicated to SSI)");
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Serial.println("\nSSI bridge ready (PIO state machine, .pio assembled)");
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Serial.println("Send: READ <bits> <half_us>");
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setStatus(0, 16, 0);
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}
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24
src/ssi.pio
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24
src/ssi.pio
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@ -0,0 +1,24 @@
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.program ssi_master
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.side_set 1
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; Side-set bit drives CLK. Idle high.
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;
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; Protocol:
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; TX FIFO: one word = (bit_count - 1)
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; RX FIFO: one word = captured bits, left-aligned in 32-bit word
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;
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; Timing: 1 PIO cycle = half of one CLK level period.
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; Each CLK level = 2 cycles, full bit period = 4 cycles.
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.wrap_target
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pull block side 1 ; wait for CPU command, CLK idle high
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out x, 32 side 1 ; X = bit_count - 1
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nop side 0 ; first falling edge: encoder latches
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nop side 0 ; latch settle (CLK still low)
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bit_loop:
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nop side 1 ; CLK rises: encoder shifts new bit
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nop side 1 ; data settles
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in pins, 1 side 0 ; CLK falls, sample
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jmp x--, bit_loop side 0 ; CLK still low, loop until done
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push block side 1 ; CLK back to idle, return result
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.wrap
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51
src/ssi.pio.h
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51
src/ssi.pio.h
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@ -0,0 +1,51 @@
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// -------------------------------------------------- //
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// This file is autogenerated by pioasm; do not edit! //
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// -------------------------------------------------- //
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#pragma once
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#if !PICO_NO_HARDWARE
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#include "hardware/pio.h"
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#endif
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// ---------- //
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// ssi_master //
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// ---------- //
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#define ssi_master_wrap_target 0
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#define ssi_master_wrap 8
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#define ssi_master_pio_version 0
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static const uint16_t ssi_master_program_instructions[] = {
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// .wrap_target
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0x90a0, // 0: pull block side 1
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0x7020, // 1: out x, 32 side 1
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0xa042, // 2: nop side 0
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0xa042, // 3: nop side 0
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0xb042, // 4: nop side 1
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0xb042, // 5: nop side 1
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0x4001, // 6: in pins, 1 side 0
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0x0044, // 7: jmp x--, 4 side 0
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0x9020, // 8: push block side 1
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// .wrap
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};
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#if !PICO_NO_HARDWARE
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static const struct pio_program ssi_master_program = {
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.instructions = ssi_master_program_instructions,
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.length = 9,
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.origin = -1,
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.pio_version = ssi_master_pio_version,
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#if PICO_PIO_VERSION > 0
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.used_gpio_ranges = 0x0
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#endif
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};
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static inline pio_sm_config ssi_master_program_get_default_config(uint offset) {
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pio_sm_config c = pio_get_default_sm_config();
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sm_config_set_wrap(&c, offset + ssi_master_wrap_target, offset + ssi_master_wrap);
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sm_config_set_sideset(&c, 1, false, false);
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return c;
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}
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#endif
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