RP2040 firmware that reads SSI absolute encoders via two MAX485 modules and streams the position over USB serial. PIO-driven (on the PIO branch), sub-µs jitter.
a8633962f2
Replace dual-core FIFO bit-bang approach with a dedicated PIO program: - Add ssi.pio: PIO assembly for SSI master (side-set CLK, sample DATA) - Add ssi.pio.h: pioasm-generated C header - ssi_pio_init(): load program, wire CLK/DATA pins, set clock divider - ssi_pio_reconfigure_speed(): live clock-divider update between reads - ssi_pio_read(): push bit-count to TX FIFO, block on RX result word - Remove dual-core headers, FIFO structs, setup1/loop1, requestSsiRead - Bit limit reduced to 1..32 (single PIO ISR word) - TX_DI pin ownership transferred to PIO (no pinMode/digitalWrite) |
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| .vscode | ||
| include | ||
| lib | ||
| src | ||
| test | ||
| .gitignore | ||
| platformio.ini | ||