lucavanstraaten 58a2d37b38 Move SSI timing-critical read to core 1 via FIFO ... - Replace hardware/sync.h with pico/multicore.h - Implement ssi_read_core1(), setup1(), loop1() on core 1 - Core 1 owns the SSI bit-bang loop; no USB/timer IRQs interfere - Core 0 sends packed request word over FIFO, receives lo32/hi32/duration - Add requestSsiRead() helper on core 0 side - Remove noInterrupts / save_and_disable_interrupts (no longer needed) - Update startup banner to reflect dual-core architecture		2026-04-28 21:03:59 +02:00
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main.cpp	Move SSI timing-critical read to core 1 via FIFO	2026-04-28 21:03:59 +02:00