Move SSI timing-critical read to core 1 via FIFO
- Replace hardware/sync.h with pico/multicore.h - Implement ssi_read_core1(), setup1(), loop1() on core 1 - Core 1 owns the SSI bit-bang loop; no USB/timer IRQs interfere - Core 0 sends packed request word over FIFO, receives lo32/hi32/duration - Add requestSsiRead() helper on core 0 side - Remove noInterrupts / save_and_disable_interrupts (no longer needed) - Update startup banner to reflect dual-core architecture
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1 changed files with 69 additions and 31 deletions
100
src/main.cpp
100
src/main.cpp
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@ -1,7 +1,7 @@
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#include <Arduino.h>
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#include <Adafruit_NeoPixel.h>
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#include <hardware/sync.h>
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#include <hardware/structs/sio.h>
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#include <pico/multicore.h>
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// CLOCK module (TX)
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const uint8_t TX_DI = 0;
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@ -23,47 +23,86 @@ Adafruit_NeoPixel led(1, LED_PIN, NEO_GRB + NEO_KHZ800);
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const uint32_t TX_DI_MASK = 1u << TX_DI;
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const uint32_t RX_RO_MASK = 1u << RX_RO;
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// Inter-core protocol
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// Request: [bits:8 | half_us:16 | reserved:8] -> core 1
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// Response: [hi32][lo32][duration_us] -> core 0
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struct SsiRequest {
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uint8_t bits;
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uint16_t half_us;
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};
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struct SsiResponse {
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uint64_t value;
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uint32_t duration_us;
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};
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void setStatus(uint8_t r, uint8_t g, uint8_t b) {
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led.setPixelColor(0, led.Color(r, g, b));
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led.show();
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}
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// SSI read with direct register I/O and interrupts disabled.
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// Single-cycle GPIO ops (~8 ns each) instead of ~1 us digitalWrite().
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// Interrupts off so USB/timer IRQs can't insert delays mid-frame.
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uint64_t ssi_read(uint8_t bits, uint16_t half_us) {
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// =========================================================================
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// CORE 1: SSI worker
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// =========================================================================
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uint64_t ssi_read_core1(uint8_t bits, uint16_t half_us) {
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uint64_t value = 0;
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// Save interrupt state and disable. save_and_disable_interrupts() returns
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// the previous state so we can restore it exactly (don't just blindly
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// re-enable - a caller higher up the stack may have wanted them off).
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uint32_t irq_state = save_and_disable_interrupts();
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// Frame start: clock idles HIGH, drop to LOW = encoder latches position
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sio_hw->gpio_clr = TX_DI_MASK;
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sio_hw->gpio_clr = TX_DI_MASK; // first falling edge: latch
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busy_wait_us_32(half_us);
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for (uint8_t i = 0; i < bits; i++) {
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sio_hw->gpio_set = TX_DI_MASK; // rising edge: encoder shifts bit
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sio_hw->gpio_set = TX_DI_MASK; // rising: encoder shifts
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busy_wait_us_32(half_us);
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sio_hw->gpio_clr = TX_DI_MASK; // falling edge: sample now
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sio_hw->gpio_clr = TX_DI_MASK; // falling: sample
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uint32_t bit = (sio_hw->gpio_in & RX_RO_MASK) ? 1 : 0;
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value = (value << 1) | bit;
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busy_wait_us_32(half_us);
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}
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// Return clock to idle HIGH
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sio_hw->gpio_set = TX_DI_MASK;
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// Re-enable interrupts before the (long) monoflop wait - no need to
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// hold them off any longer, the timing-critical part is done.
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restore_interrupts(irq_state);
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busy_wait_us_32(30); // monoflop reset time
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sio_hw->gpio_set = TX_DI_MASK; // back to idle
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busy_wait_us_32(30); // monoflop
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return value;
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}
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void setup1() {
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// Core 1 setup: nothing to do, GPIOs already configured by core 0.
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// Importantly: no Serial, no USB, no millis IRQ active here by default
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// when running in this dual-core mode.
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}
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void loop1() {
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// Block until core 0 sends a packed request word.
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// Word layout: bits in upper 8, half_us in next 16, 8 unused
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uint32_t req = rp2040.fifo.pop();
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uint8_t bits = (req >> 24) & 0xFF;
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uint16_t half_us = (req >> 8) & 0xFFFF;
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uint32_t t0 = time_us_32();
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uint64_t value = ssi_read_core1(bits, half_us);
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uint32_t took = time_us_32() - t0;
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// Push three words back: low32, high32, duration
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rp2040.fifo.push((uint32_t)(value & 0xFFFFFFFF));
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rp2040.fifo.push((uint32_t)(value >> 32));
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rp2040.fifo.push(took);
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}
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// =========================================================================
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// CORE 0: serial command handler
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// =========================================================================
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void requestSsiRead(uint8_t bits, uint16_t half_us, uint64_t& outValue, uint32_t& outTook) {
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uint32_t req = ((uint32_t)bits << 24) | ((uint32_t)half_us << 8);
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rp2040.fifo.push(req);
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uint32_t lo = rp2040.fifo.pop();
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uint32_t hi = rp2040.fifo.pop();
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outTook = rp2040.fifo.pop();
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outValue = ((uint64_t)hi << 32) | lo;
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}
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void handleCommand(const String& cmd) {
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if (!cmd.startsWith("READ ")) {
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Serial.println("ERR unknown command. Use: READ <bits> <half_us>");
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@ -90,13 +129,13 @@ void handleCommand(const String& cmd) {
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}
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setStatus(0, 0, 16); // blue = reading
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uint32_t t0 = micros();
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uint64_t raw = ssi_read(bits, halfUs);
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uint32_t elapsed = micros() - t0;
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uint64_t value;
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uint32_t took;
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requestSsiRead((uint8_t)bits, (uint16_t)halfUs, value, took);
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setStatus(0, 16, 0); // green = idle
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Serial.printf("OK bits=%d half_us=%d hex=0x%llX dec=%llu took=%luus\n",
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bits, halfUs, raw, raw, elapsed);
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bits, halfUs, value, value, took);
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}
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void setup() {
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@ -110,18 +149,17 @@ void setup() {
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pinMode(RX_DI, OUTPUT);
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pinMode(RX_RO, INPUT);
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digitalWrite(TX_DE, HIGH); // CLK module = transmit
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digitalWrite(TX_DE, HIGH);
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digitalWrite(TX_RE, HIGH);
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digitalWrite(RX_DE, LOW); // DATA module = receive
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digitalWrite(RX_DE, LOW);
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digitalWrite(RX_RE, LOW);
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digitalWrite(RX_DI, LOW);
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digitalWrite(TX_DI, HIGH); // SSI clock idles HIGH
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digitalWrite(TX_DI, HIGH); // SSI idle HIGH
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delay(200);
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while (!Serial && millis() < 3000) { delay(10); }
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Serial.println("\nSSI bridge ready (B+C: direct registers, IRQs off during read)");
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Serial.println("\nSSI bridge ready (dual-core: core 1 dedicated to SSI)");
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Serial.println("Send: READ <bits> <half_us>");
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Serial.println("Example: READ 25 5");
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setStatus(0, 16, 0);
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}
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